
Omkar Rajendra Palaskar
Summary: - Graduate student at San Jose State University with specialization in Digital VLSI. - Experience working in Hardware Design for FPGA,... | Austin, Texas, United States
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Omkar Rajendra Palaskar’s Emails om****@nx****.com
Omkar Rajendra Palaskar’s Phone Numbers 1408434****
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Omkar Rajendra Palaskar’s Location Austin, Texas, United States
Omkar Rajendra Palaskar’s Expertise Summary: - Graduate student at San Jose State University with specialization in Digital VLSI. - Experience working in Hardware Design for FPGA, Hardware Test and Software Engineering. - Good understanding of ASIC Design flow, writing RTL models and testbenches in Verilog, SystemVerilog, and UVM, Functional testing, memory controller (DDR) design, and verification. - Knowledge of functional verification, coverage-driven verification, and assertion-based verification. Skills: ● Languages: C, C++, VHDL, Verilog, System Verilog,UVM ● Scripting Languages: Python ● EDA Tools: Xilinx ISE, Xilinx Vivado, Modelsim, Synopsys VCS, Synopsys Design Compiler, NCVerilog, Cadence Virtuoso ● Design/Verification skills: RTL coding, Simulation, Synthesis, Static timing analysis (STA), CMOS logic, Assertions, SVOOPs ● Protocols: (AMBA- APB, AHB, AXI Stream), I2C, UART, SPI ● Hardware boards: Basys 2 (Spartan‐3E), Basys 3(Artix‐7) Contact: Email: [email protected] Cell: +1 669 281 9576
Omkar Rajendra Palaskar’s Current Industry Nxp Semiconductors
Omkar
Rajendra Palaskar’s Prior Industry
Accenture
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San Jose State University
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Granite River Labs
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Lewiz Communications
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Analog Devices
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Nxp Semiconductors
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Work Experience

Nxp Semiconductors
Senior Design Verification Engineer
Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Analog Devices
Digital Design Engineer
Thu Aug 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Feb 01 2022 00:00:00 GMT+0000 (Coordinated Universal Time)
Lewiz Communications
Hardware Design Intern
Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed May 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Granite River Labs
Hardware Test Intern
Fri Jun 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Aug 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
San Jose State University
Instructional Student Assistant
Thu Feb 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue May 01 2018 00:00:00 GMT+0000 (Coordinated Universal Time)
Accenture
Software Engineer
Fri Aug 01 2014 00:00:00 GMT+0000 (Coordinated Universal Time) — Wed Jun 01 2016 00:00:00 GMT+0000 (Coordinated Universal Time)